1. Field of the Invention
The present invention relates to the field of semiconductor processing, and more particularly to a method for utilizing a local interconnect and connecting the local interconnect to an underlying transistor level.
2. Description of the Relevant Art
Integrated circuits are widely employed in a variety of electronics applications to produce complex electronics circuits on an extremely small area of a monolithic semiconductor substrate, such as silicon. Universally recognized for their low cost, high speed, low power dissipation, and high reliability, semiconductor integrated circuits long ago replaced discreet components as the preferred electronic devices for most electronics applications. World-wide sales of integrated circuits have increased exponentially since the early 1960s. During this time, semiconductor manufacturers have striven to reduce the cost and increase the complexity of integrated circuits by fabricating a larger number of transistors in a given area of the semiconductor substrate. The primary means of achieving these goals has been reducing the size of the individual transistors that comprise the integrated circuit. Smaller transistors enable the fabrication of more complex and smaller devices. Smaller devices increase the number of devices manufacturable on a single semiconductor wafer and increase the probability that any individual device on a given silicon wafer will be free of random fatal defects. Since the early 1960's, when the average design rule within the industry was approximately 25 microns, the average design rule has decreased rather steadily by approximately 11% per year. The average design rule dropped below one micron in the mid 1980s, and has been decreasing steadily since then.
Transistor geometries on many semiconductor processes are now in the deep submicron region. Additional miniturization of transistor geometries is becoming increasingly difficult and costly to achieve. In response, semiconductor manufacturers are constantly seeking alternative methods of increasing transistor density to enable the cost effective production of ever increasingly complex integrated circuits. One such method involves the fabrication of a multi-layer transistor structure. In this method, a second transistor level is fabricated on a first transistor level to minimize the percentage of the silicon substrate devoted to transistor isolation. Multi-layer transistor structures are disclosed and claimed in a pending U.S. patent application entitled "Transistor Formation for Multi-Level Transistors" by Mark Gardner and filed on Sep. 30, 1996, [hereinafter referred to "the prior application"]. This application is incorporated by reference herein. Although the prior application discloses a method of increasing transistor density, it did not suggest a method of connecting features of the upper transistor level with features of the lower transistor level. A person of ordinary skill would typically form interconnects from the upper transistor level to the lower transistor level in a conventional fashion by forming a contact hole in an interlevel dielectric above the first transistor level and filling the hole with a conductive material such as aluminum or copper. This conventional method of interconnecting two levels of the integrated circuit requires the deposition of an additional interlevel dielectric and the formation of an independent interconnect level thereby adding increased complexity and cost to the semiconductor process. In addition, such a contact structure would be susceptible to junction spiking and other reliability issues. Accordingly, it would be beneficial to implement a more reliable semiconductor process in which a second interconnect level could be connected to an underlying first transistor level without unduly increasing the complexity or cost of the process.